1. Field of the Invention
The invention relates to a method of ensuring synchronization of a data block in a receiver. In the method, a first bit sequence of alternating logic "0" and "1" levels is transmitted consecutively prior to the block. The first sequence is for determining the bit clock for the bits of the data block. A second bit sequence is also transmitted consecutively prior to the block. The second bit sequence is for determining synchronization of the block by correlation with a bit sequence stored in the receiver.
2. Prior Art
In digital information systems operating with block-wise transmission of information, the receiver has to be synchronized with the transmitter so that a common starting instant for the two arrangements is established. For synchronizing the receiver with the transmitter, a specific bit pattern can be produced in the transmitter and transmitted to the receiver. For establishing the starting instant the receiver derives a criterion by correlating the received data signal with a stored data signal.
If, as frequently happens with radio transmission links, interference in the transmission path causes bit errors that lead to relatively high bit error rates, the received bit pattern cannot always be recognized if one or more bits of the pattern are distorted on the transmission path.
Such a bit pattern preceding the data block proper is, for example, a first bit sequence of alternating half-bits for determining the bit clock for the bits of the data block and a second bit sequence for determining the block synchronization by correlation with the bit sequence stored in the receiver, as shown in U.S. Pat. No. 3,591,720.
The German Patent DE-PS No. 22 19 016 discloses a method of synchronizing the clock phase in a receiver to the phase position of the bit clock of a received data block; for simultaneously determining the bit clock and the block synchronization according to this method, the bit sequence is applied to N parallel-arranged correlators, whose associated shift registers are controlled by mutually offset shift-clock pulse sequences.
Recovering the bit clock and the block synchronization from the received data signal is hampered by the influence of noise voltages, transients and fading and the phase jitter resulting therefrom, so that the phase synchronization is relatively inaccurate or unattainable within a relatively short time interval. Furthermore, the circuit implementation is relatively complex owing to the correlator bank and, without further measures, it is not possible to determine the instant at which correlation signals have to be evaluated, for example for avoiding erroneous synchronization due to noise.
In addition, the published German Patent Application DE-OS No. 30 12 075 discloses a circuit arrangement for bit synchronization, in which also the bit clock is derived from the received data signal. For this purpose, the overall phase range of the individual bits (from 0 to 360 degrees) is divided into sub-intervals (so-called phase windows). During a measuring interval the number of occurrences of the instantaneous phase values assigned to sub-intervals are stored (by means of edge counters). The number of sub-intervals (phase windows) is determined by a divider circuit in combination with AND circuits. These circuits produce pulse sequences that are phase-shifted according to the reciprocal value of the number of different phase windows.
Counters are connected to the outputs of these circuits in order to count the number of edges of the received data signal that have fallen in the associated sub-interval (phase window). At the end of the measuring interval the phase of the bit clock is corrected by an estimated phase value corresponding to the phase value of the sub-interval having the largest number of edges.
For this purpose, a higher bit clock is supplied to the counters via a divider circuit and change-over switches at the end of the measuring interval, whereby the up-counting is accelerated. Owing to the phase-shifted pulse sequences there will always be only a single counter that reaches the maximum position, and by means of a subsequent code converter a binary number can be assigned to the counting position, which binary number is stored in a memory. Switching-over and reading-out the stored binary number that corresponds to the sub-interval having the largest number of edges and hence to the phase-synchronous bit clock, is controlled by a control logic and the received bit clock is corrected according to the estimated value of the phase.
Such a circuit arrangement has the disadvantage that as a consequence of the recovery of the bit clock from the received data signal the phase jitter of this data signal, i.e. the fluctuation of its significant instants around instants that are equidistant ideally, has its effects on the determination of the estimated value of the phase. More specifically, in radio transmission links frequent re-synchronization will be required as the bit error rate will assume inadmissibly high values as a result of fading.